The present invention generally relates to computing systems, and, more particularly, to an interrupt management system for a computing system.
Computing systems include a processor, multiple peripheral devices connected to the processor, and an interrupt controller connected between the peripheral devices and the processor. Examples of such computing systems include computer systems, consumer electronic devices, and communication network elements.
The peripheral devices generate multiple interrupts and corresponding interrupt signals that indicate occurrences of events to be serviced by the processor. The interrupt controller receives the interrupt signals and transmits them to the processor. Interrupts are of two types—real-time and non-real-time interrupts. A real-time interrupt is a time-critical interrupt. Generally, the real-time interrupt is a high-priority interrupt and must be serviced by the processor within a predetermined time period. Non-real-time interrupts include maskable and non-maskable interrupts. A maskable interrupt is a low priority interrupt and a non-maskable interrupt is a high-priority interrupt. A non-maskable interrupt has higher priority than a real-time interrupt.
When the processor receives a real-time interrupt signal, the processor executes an interrupt service routine (ISR) corresponding to the real-time interrupt and a non-ISR program corresponding to the real-time interrupt (collectively referred to as “real-time program”). The ISR and the non-ISR program, both corresponding to the real-time interrupt, must be executed by the processor within the predetermined time period. When the processor receives a non-real-time interrupt signal corresponding to a non-real-time interrupt, the processor executes an ISR and a non-ISR, both corresponding to the non-real-time interrupt (collectively referred to as “non-real-time program”).
When the processor receives the non-real-time interrupt signal during the execution of the real-time program, the processor suspends the execution of the non-ISR program corresponding to the real-time interrupt and executes the ISR corresponding to the non-real-time interrupt. The processor resumes the execution of the real-time program after executing the ISR corresponding to the non-real-time interrupt, thereby delaying execution of the real-time program. Further, the processor may receive multiple non-real-time interrupt signals during the predetermined time period. Hence, the processor may fail to complete the execution of the real-time program within the predetermined time period, which reduces the efficiency of the computing system.
For example, if the processor is part of an eNode-B, then the processor executes a layer-2 (L2) stack of a long term evolution (LTE) communication system protocol. The processor is connected to multiple peripheral devices, such as a universal serial bus (USB) port, a universal asynchronous receiver/transmitter (UART), and a serial peripheral interface (SPI) bus. The eNode-B further includes an antenna interface controller (AIC) that generates a periodic real-time interrupt. The periodic real-time interrupt is referred to as transmission time interval (TTI) signal and the time period of the TTI signal is the transmission time interval (TTI) window. The processor receives the TTI signal and executes a real-time program corresponding to the TTI signal. The processor must finish the execution of the real-time program, e.g., the LTE L2 stack, within the TTI window. Failure to finish the execution of the real-time program within the TTI window results in to an LTE protocol violation. Further, the other peripheral devices may generate non-real-time interrupts, which are sent to the processor. When the processor receives a non-real-time interrupt during execution of the real-time program, the processor suspends execution of the real-time program indicated by the TTI signal. Further, the processor executes an ISR corresponding to the non-real-time interrupt. The processor resumes execution of the real-time program after execution of the non-real-time interrupt ISR. This delays completion of the real-time program, which increases the probability of an LTE protocol violation.
One known technique to overcome the probability of a protocol violation includes use of a real-time interrupt period (RTIP) counter and multiple safe-period counters. The RTIP counter stores an RTIP value and generates a real-time interrupt signal after a time period indicative of the stored RTIP value. Similarly, each safe-period counter stores a safe-period value and generates a safe-period signal after the time period indicative of the stored safe-period value. Further, each safe-period signal corresponds to a non-real-time program. The processor receives the safe-period signals and suspends execution of corresponding non-real-time programs. The processor then receives the real-time interrupt signal and executes an ISR corresponding to the real-time interrupt. The processor then resumes the non-real-time programs after receiving the real-time interrupt signal and re-initializes the RTIP and safe-period counters. Hence, the technique suppresses the non-real-time programs before the generation of the real-time interrupt signal. However, the technique does not reduce interference of the non-real-time interrupts during the execution of the real-time interrupt ISR.
In another known technique, where multiple interrupts are generated by a peripheral device during a predetermined time period, transmission of the interrupts to the processor is inhibited during the predetermined time period and the interrupts are stored in a register of the peripheral device. After the predetermined time period, the processor reads a value of the register and executes corresponding ISRs. Further, the processor inhibits generation of the interrupts by the peripheral device for the predetermined time period after reading the register. However, this technique does not distinguish between real-time and non-real-time interrupts.
It would be advantageous to have a system that manages interrupts, and ensures completion of real-time programs uninterruptedly within a predetermined time period.